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How to read clock cycle from latency tables?
I see many papers that compare the latency of the signature schemes in terms of clock cycles by two-three numbers. I don’t know why they write 2-3 numbers instead of one number to represent clock cycle. For example consider the following table from this paper link: https://eprint.iacr.org/2019/122.pdf
I see many papers that compare the latency of the signature schemes in terms of clock cycles by two-three numbers. I don’t know why they write 2-3 numbers instead of one number to represent clock cycle. For example consider the following table from this paper link: https://eprint.iacr.org/2019/122.pdf
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